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Characterization

Concept of Degradation-Free Transistor :

Time-dependent change in threshold voltage, due to generation of interface/bulk traps, degrades drain current of field effect transistors. In this paper, we show – both theoretically and experimentally – the intriguing possibility of designing degradation-free transistors (with time-invariant drain-current), where the degradation in threshold voltage is exactly compensated by improvement in mobility. Such transistors would reduce parametric reliability being a key concern for supply voltage scaling and thereby improve integrated circuit performance by minimizing the guard band voltage used in Very Large Scale Integrated (VLSI) circuit design.

Related Publications:

§ A. E. Islam, and M. A. Alam, “On the Possibility of Degradation-Free Field Effect Transistors”, Applied Physics Letter, 92, 173504, April 2008.

§ A. E. Islam, and M. A. Alam, “Field Effect Transistors Having Negligible Drain Current Degradation”, Patent Pending (Submitted: March 5, 2008).

Mobility Characterization:

Mobility degradation due to generation of interface traps (Dm_eff(N_IT)) is a well-known phenomenon that has been theoretically interpreted by several mobility models. Based on these analysis, there is a general perception that Dm_eff(N_IT) is relatively insignificant (compared to Dm_eff due to ionized impurity) and as such can be safely ignored for performance and reliability analysis. We have investigated the importance of considering Dm_eff(N_IT) for reliability analysis by analyzing a wide variety of plasma oxynitride PMOS devices using both parametric and physical mobility models. We find that contrary to popular belief this correction is fundamentally important for robust and uncorrupted estimates of the key reliability parameters like threshold-voltage shift, lifetime projection, voltage acceleration factor, etc. Therefore, we develop a generalized algorithm for estimating Dm_eff(N_IT) for plasma oxynitride PMOS devices and systematically explore its implications for NBTI-specific reliability analysis.

Estimation of V_T Degradation for Modern NBTI Characterization Techniques:

On-the-fly and Ultra-fast V_T are popular characterization techniques for analyzing NBTI degradation. We show that these techniques do not probe the intrinsic NBTI degradation directly and hence require suitable correction. The ‘corrected’ data allows us to explore the subtlety of relaxation dynamics by various measurements.

Related Publications:

§ A. E. Islam, V. D. Maheta, H. Das, S. Mahapatra, and M. A. Alam, “Mobility Degradation Due to Interface Traps in Plasma Oxinitride PMOS Devices”, IRPS 2008, Apr 2008, pp. 87-96. (Breeze Presentation)

§ A. E. Islam, E. N. Kumar, H. Das, S. Purawat, V. D. Maheta, H. Aono, E. Murakami, S. Mahapatra, and M. A. Alam, “Theory and Practice of On-the-fly and Ultra-fast V_T Measurements for NBTI Degradation: Challenges and Opportunities”, IEDM Tech. Digest, pp. 805-808, December 2007. (Nominated for Roger A. Haken Best Student Paper Award)

Optimization Between Gate Leakage and NBTI for Nitrided Devices:

Reduction in static power dissipation (gate leakage) by using nitrided oxides comes at the expense of enhanced Negative Bias Temperature Instability (NBTI). Therefore, determining the nitrogen content in gate oxides that can simultaneously optimize gate leakage and NBTI degradation is a problem of significant technological relevance. Here, we experimentally and theoretically analyze wide range of gate leakage and NBTI-stress data from a variety of plasma oxynitride gate dielectric devices to establish an optimization scheme for gate leakage and NBTI degradation. Calculating electric fields and leakage current both numerically and using simple analytical expressions, we demonstrate a design diagram for arbitrary nitrogen concentration and effective oxide thickness that may be used for process- and IC- design.

Related Publications:

§ A. E. Islam, G. Gupta, K. Ahmed, S. Mahapatra, M. A. Alam, “Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models”, IEEE TED, 55(5), pp. 1143-1152, May 2008.

§ A. E. Islam, G. Gupta, S. Mahapatra, A. T. Krishnan, K. Ahmed, F. Nouri, A. S. Oates, and M. A. Alam, “Gate Leakage vs. NBTI for Plasma Nitrided Oxides: Characterization, Physical Principles and Optimization”, IEDM Tech. Digest, pp. 12.4.1, December 2006.

Characterization of Circuit Reliability Using I_DDQ Measurement:

An efficient technique to characterize and estimate the lifetime circuit reliability under NBTI degradation. Unlike conventional approaches, where a representative f_MAX (maximum operating frequency) measurement from timing critical circuitry is used, we propose to utilize the standby circuit leakage I_DDQ as a metric to detect and characterize temporal NBTI degradation in digital circuits. Compared to the f_MAX based approach, the proposed I_DDQ based technique benefits from lower test cost and improved capability of estimating reliability of complex circuitries such as ALUs and SRAM arrays. The proposed model is verified with measurement data obtained from a test chip fabricated in 130nm technology. Furthermore, we examine the possible applications of our proposed I_DDQ based NBTI characterization. We show that the temporal degradation in static noise margin (SNM) of SRAM array and f_MAX of random logic circuits are highly correlated to the I_DDQ measurement, and this relationship can be used to predict long term circuit reliability.

Related Publication:

§ Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad A. Alam, and Kaushik Roy, “Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line I_DDQ Measurement”, Proceedings of 44th Design Automation Conference, 20.1, June 2007.

Dielectric Capacitance Determination:

Dielectric capacitance (C_ox or, C_di) estimation for MOS devices is of foremost importance in characterizing MOS devices. It is normally expressed in terms of effective oxide thickness (EOT = e_SiO2/C_ox), which is necessary to be correctly determined before starting any further analysis with MOS devices. Henceforth, C_ox determination is extensively studied previously mostly using semi-classical approach (e.g. techniques proposed by McNutt/Shah and also by Maserjian). These semi-classical approach, although was very effective for devices having EOT above 3nm, should fail for sub 0.1mm devices having High-K dielectric. The main reason for such failure comes from the quantization of confined carriers in the channel of these devices. Such quantization effect leads to finite values for semiconductor capacitance (C_sc) compared to its very high value under semiclassical approximation (both in inversion and accumulation region of MOS devices). Finite value for C_sc, being comparable with C_ox (both being in series connection in a MOS structure), thus makes C_ox determination more challenging for sub 0.1 mm devices. Using moderate to strong accumulation region C_G-V_G curve for a MOS structure, we have shown that C_ox determination indeed becomes possible based on an assumed of dependence of C_sc in accumulation region. The dependence of C_sc is based on exact quantum mechanical (QM) treatment of MOS electrostatics. The proposed C_ox extraction technique is as simple as the semi-classical techniques used for MOS structures having less QM effect. More importantly, its prediction is as good as the values obtained using the fit of C_G-V_G curves using QMCV simulators, which are computationally extensive. The proposed technique is verified with different QMCV models (e.g. for simulators like those developed by the BUET group, UT-Austin group and NCSU group) and the matching is excellent, on the condition that leakage is not affecting the C_G-V_G regions under analysis (guaranteed for sub-0.1mm MOS device having High-K dielectric). We hope that this technique will help extensively in quick C_ox characterization of the samples.

Related Publication and Presentation:

§ A. E. Islam, A. Haque, “Accumulation gate capacitance of MOS devices with ultra-thin high-K gate dielectrics: Modeling and Characterization”, IEEE TED, 53(6), pp. 1364-1372, June 2006.

§ Accumulation C_G of MOS devices with ultra-thin high-K gate dielectrics: Modeling and Characterization: Presentation Explaining the Technique

Modeling

Modeling Interface Trap Generation

Modeling of Interface Trap (N_IT) generation is performed within Reaction-Diffusion (R-D) framework, which involves breaking (reaction) of SiH bonds (at oxide/substrate interface) and subsequent diffusion of resultant H-species (H and H₂) through oxide dielectric and poly-Si gate. My contribution here involves analytical solution of R-D model, representing N_IT generation at constant voltage stress [TED ‘07]. The analytical formalism captures the time dynamics of N_IT generation, which is also verified using detailed numerical simulation. I have also identified experimental signatures (using electric field and temperature dependent study [IEDM ’06, TED ‘07], and m_eff study [IRPS ‘08) of NBTI for nitrided devices) of hole tunneling into N_IT and subsequent barrier lowering for Si-H bond dissociation (making N_IT generation easier) as the origin of N_IT generation. The proposed mechanism [IEDM ’06, TED ‘07] provides first self-consistent study of dangling bond generation within R-D framework.

Modeling Trapping into Pre-existing Oxide Traps

Modeling efforts on hole trapping into pre-existing oxide traps identified the mechanism to be dominant only in devices having thick oxynitride gate dielectric with higher nitrogen concentration near oxide/substrate interface [TED ’07, IRPS ’07, IEDM ‘07]. Moreover, based on our Shockley-Read-Hall analysis, trapping into pre-existing traps is expected to saturate quickly within ~msec timeframe, which is also verified using detailed experimental study [TED ’07, IRPS ’07, IRPS ‘08].

Related Publications:

Journals

§ A. E. Islam, H. Kufluoglu, D. Varghese, S. Mahapatra, and M. A. Alam, “Recent Issues in Negative Bias Temperature Instability: Initial Degradation, Field-Dependence of Interface Trap Generation, and Hole Trapping Effects and Relaxation”, (Invited Paper) IEEE TED (Special Issue on Modeling of Nanoscale Transistors), 54(9), pp. 2143-2154, Sep 2007.

§ A. E. Islam, H. Kufluoglu, D. Varghese, and M. A. Alam, “Critical Analysis of Short-term Negative Bias Temperature Instability Measurements: Explaining the effect of time-zero delay for On-the-fly Measurements”, Applied Physics Letter, 90, 083505 (2007).

Conference Proceedings

§ J. H. Lee, W. H. Wu, A. E. Islam, M. A. Alam and A. S. Oates, “Separation method of hole trapping and interface trap generation and their roles in NBTI Reaction-Diffusion model”, IRPS 2008, Apr 2008, pp. 745-746.

§ E. N. Kumar, V. D. Maheta, S. Purawat, S. Rani, A. E. Islam, K. Ahmed, M. A. Alam and S. Mahapatra, “Material Dependence of NBTI Physical Mechanism in Silicon Oxynitride (SiON) p-MOSFETs: A Comprehensive Study by Ultra-Fast On-The-Fly (UF-OTF) IDLIN Technique”, IEDM Tech. Digest, session 31.4, December 2007.

§ S. Mahapatra, K. Ahmed, D. Varghese, A. E. Islam, G. Gupta, L. Madhav, D. Saha and M. A. Alam, “On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy?”, IRPS Tech. Digest, pp. 1-9, April 2007.

MOS Electrostatics Modeling Through QM Simulation:

As mentioned earlier, quantum-mechanical effects like carrier quantization in quasi-bound states near the dielectric/substrate interface of MOS devices is getting quite important for nanoscale devices. Such modeling also shows significant amount of carrier leakage in sub-0.1 um devices, a signature of energy broadening of the confined carriers. I have worked in modeling these effects, which is implemented using the so-called Non-equilibrium Green’s Function (NEGF) approach. Device simulation by NEGF in discrete space domain is done within the framework of Finite Difference Method (FDM). The related works are published in IEEE TED, 53(6), pp. 1364-1372, June 2006.