EDUCATION
PhD [08/2006-present]: School of ECE, Purdue University, IN, USA
Primary Research Area: VLSI Circuit/Architecture Design (Si and Spintronics)
Secondary Research Area: Evaluation Framework for Charge/Non-Charge Device Technologies
Advisor: Prof. Kaushik Roy
Thesis: “Developing device-circuit-architecture framework for Charge(more Moore – MOSFET)/Non-charge(beyond Moore – nano-magnet, all-spin, spin-torque) based logic and memory technologies”

Graduate Courses: Advanced VLSI Design, Quantum Transport: Atom to Transistor, Solid State Devices, Analog VLSI Design, Digital Signal Processing, Computer Architecture, Linear Algebra, Advanced Math for Engineers.

Bachelors [08/2000-06/2004]: Electronics & Instrumentation, Birla Institute of Technology & Science, Pilani, India
CGPA: 9.96/10
Research Area: Low Power VLSI Design
Advisor: Dr. Subhendu Kumar Sahoo
Thesis: “Parallel multiplier exploration & design for high speed, low power, low cost and small area”

PROFESSIONAL EXPERIENCE

  • Research Assistant – Nano Research Lab (Prof. Kaushik Roy), ECE, Purdue University (Aug 2006 - present).

  • Research Intern – Freescale Semiconductors, Austin, TX (May 2008 – Aug 2008).

  • Design Engineer – Philips Semiconductors India Pvt Ltd, Bangalore, India (July 2005- July 2006)

  • Design Engineer – Texas Instruments India Pvt Ltd, Bangalore, India (June 2004 – July 2005)

  • Research Intern – ST Microelectronics India Pvt Ltd, Noida, India (Jan 2004 – June 2004)

  • Research Intern – Bhabha Atomic Research Center, Bombay, India (May 2002 – July 2004)



RESESARCH INTEREST
Development of device-circuit-architecture framework for Charge (more Moore – MOSFET)/Non-charge (beyond Moore - nano-magnet, all-spin, spin-torque) based logic and memory technologies.

ACADEMICH ACHIEVEMENTS

  • Received "Best Paper in Session Award" at SRC Techcon 2009 for the paper titled “A Comprehensive Nano-magnet Based Logic Synthesis for Ultra-Low Power Digital Systems.”

  • Received "AMD Design Excellence Award" for the Adv. VLSI Design class at Purdue University for the project titled “Complimentary Ferroelectric Capacitor (CFC) Logic: Application to TAG RAM”, 2008.

  • Received Bronze medal from Birla Institute of Technology and Science, Pilani for the academic year 2003-2004 (Out of 900 students).

  • Received "S. S. Seshadri Memorial Scholarship" award for two consecutive semesters at BITS-Pilani, and also received "University Merit Scholarship" on remaining six semesters at BITS-Pilani.

  • Received Design Automation Conference Young Student Support Program (YSSP)'08 and Design Automation Summer School (DASS)'09 awards.

  • Merit list holder of Central Board of Secondary Education (CBSE) 2000.


PAPERS PUBLISHED IN SCIENTIFIC FORUMS

Conferences

  • C. Augustine, X. Fong, B. Behin-Aein, K. Roy, “A Comprehensive Nano-magnet Based Logic Synthesis for Ultra-Low Power Digital Systems”, SRC TECHCON 2009 (Best Paper in Session Award).

  • C. Augustine, A. Raychowdhury, Y. Gao, M. Lundstrom, K. Roy, “A Device/Circuit Analysis Framework for Evaluation and Comparison of Charge Based Emerging Devices”, ISQED‟09 (Best Paper Nomination).

  • C. Augustine, B. Behin-Aein and K. Roy, “Nano-Magnet Based Ultra-Low Power Logic Design Using Non-Majority Gates”, IEEE-Nano, 2009.

  • C. Augustine, B. Behin-Aein, X. Fong, K. Roy, “A Design Methodology and Device/Circuit/Architecture Compatible Simulation Framework for Low-Power Magnetic Quantum Cellular Automata Systems”, ASP-DAC‟09.

  • J. Kulkarni, C. Augustine, B. Jung, K. Roy, “Nano-Spiral Inductors for Low Power Digital Spintronic Circuits”, IEEE International Magnetic Conference, 2009.

  • N. Banerjee, C. Augustine, K. Roy, “Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and its Application to Digital Signal Processing Systems”, DFT‟08.

  • J. Li, C. Augustine, S. Salahuddin. K. Roy, “Modeling of Failure Probability and Statistical Design of Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) Array for Yield Enhancement”, IEEE DAC‟08.

  • A. Raychowdhury, C. Augustine, Y. Gao, M. Lundstrom, K. Roy, “Purdue Emerging Technology Evaluator (PETE): A Device/Circuit Analysis Framework for Comprehensive Assessment of Emerging Devices”, SRC TECHCON 2008.


Journals

  • C. Augustine, X. Fong, B. Behin-Aein, K. Roy, “Ultra-low Power Nano-magnet Based Computing: A System-Level Perspective,” to be submitted in IEEE Tran. on Nano.


RESESARCH COMMUNITY MEMBERSHIPS

  • Semiconductor Research Corporation (SRC)

  • Gigascale System Research Center (GSRC)

  • Nano Research Initiative (NRI)

  • IEEE Student Member


DETAILED RESUME:Charles_Augustine_Resume_2010