Purdue University, PhD ECE in progress,  2008 - now, 4.0/4.0

 Shanghai Jiaotong University, BS ECE,    2002 - 2006, 3.8/4.0

 

 

 

      Fabrication of the All Spin Logic (ASL) devices. We fabricated the lateral graphene spin valves structure as a first step and observed the longest spin relaxation length (~5um) at room temperature. (PhD)

      Simulation of Spin Transfer Torque (STT) with Landau-Lifshitz-Gilbert (LLG) equation. (PhD)

      Simulation of spin-field effect transistors (spinFETs) with real structure and spin relaxation. (PhD)

      Systematic study of carbon-based tunneling field effect transistors (TFETs) and circuit level benchmark against 15nm CMOS. (MSEE)

      Quantum memory device modeling. (BSEE)

  

 

 

   Y. Gao, Y. Kubo, et al., “Optimized Spin Relaxation Length in Few Layer Graphene at Room Temperature”, IEDM 4-4, 2012

   Y. Gao, et al., “Simulating Realistic Implementations of SpinFET”, J. Appl. Phys. 109, 7, 2011

   Y. Gao, et al., “Simulation of the SpinFET: Effects of Tunneling and Spin Relaxation on Performance”, J. Appl. Phys. 108, 8, 2010

   Y. Gao, et al., “Realistic SpinFET Performance Assessment for Reconfigurable Logic Circuits”, VLSI Tech, 2010

   Y. Gao, et al., “Possibility for Vdd=0.1V Logic Using Carbon-Based Tunneling FETs”, VLSI Tech, 2009