08/05– 12/05::   ECE495D:  ASIC DESIGN LAB

01/06– 05/06::   ECE495D:  ASIC DESIGN LAB

08/06– 12/06::   ECE337:  ASIC DESIGN LAB

01/07– 05/07::   ECE337:  ASIC DESIGN LAB

 

 

 

 

 

 

 

 

 

 

 

 

© gkarakon@purdue.edu

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Georgios Karakonstantis

Phd Candidate

Electrical & Computer Enineering

Nanoelectronics Research Laboratory  ( NRL)

Purdue University

Description: Introduction to standard cell design of VLSI (Very Large Scale Integration) digital circuits using the VHDL hardware description language (Very High Speed Integrated Circuits Hardware Description Language). Emphasis on how to write VHDL that will map readily to hardware. Laboratory experiments using commercial grade computer-aided design (CAD) tools for VHDL based design, schematic based logic entry, logic and VHDL simulation, automatic placement and routing, timing analysis, and testing.

Lab 150 minutes/week .

Responsible for 1h lecture , 2h lab assignments and grading.

© G. Karakonstantis

      Diploma Thesis

Monday, July 13, 2009