Journals

 

· G. Karakonstantis, N. Banerjee, and K. Roy, “Process-Variation Resilient & Voltage-Scalable DCT Architecture for Robust Low-Power Computing,” to appear in IEEE Tran. on VLSI 2009.

 

·     N. Banerjee, G. Karakonstantis, J.H. Choi, C Chacrabarti and K. Roy, “Design Methodology for   

      Low Power Dissipation and Parametric Robustness through Output Quality Modulation:

      Application to Color Interpolation Filtering,” to appear in IEEE Tran. on CAD, 2009.

 

·     S. Ghosh, D. Mahapatra, G. Karakonstantis and Kaushik Roy, “Low-power and robust circuit   

   design under parameter variations using critical path isolation and adaptive clocking”, to appear

    in IEEE Trans on VLSI, 2009 .

 

Conferences

 

· G. Karakonstantis, D. Mohapatra, K. Roy, “System Level DSP Synthesis Using Voltage Overscaling, Unequal Error Protection & Adaptive Quality Tuning: Application to DCT/IDCT,”

      IEEE SIPS, 2009.

 

· D. Mohapatra , G Karakonstantis, K. Roy, “Significance. Driven Computation: A Voltage-Scalable, Variation-Aware, Quality-Tuning Motion Estimator,” IEEE ISLPED, 2009.

 

· G. Karakonstantis, K. Roy, “Algorithm/Architecture Co-Design for Low Power and Parametric Robustness through Adaptive Quality Modulation”, ACM Phd Forum, IEEE DAC, 2009.

 

· G. Karakonstantis, N. Banerjee, K. Roy, C. Chakrabarti,  “Design Methodology to trade off Power,

    Output Quality and Error Resiliency: Application to Color Interpolation Filtering”, IEEE ICCAD,     

     November 2007.

     pdf

· D. Mohapatra, G. Karakonstantis, K. Roy, “Low-Power Process-Variation Tolerant Arithmetic Units Using Input-Based Elastic Clocking” , IEEE ISLPED, August 2007.

     pdf

· G. Karakonstantis, K. Roy, “An Optimal Algorithm for Low Power Multiplierless FIR Filter Design using Chebychev Criterion”, IEEE ICASSP, Volume 2, Page(s):II-49 - II-52, 2007, April 2007.

     pdf

· N. Banerjee, G. Karakonstantis, K. Roy, “Process Variation Tolerant Low Power DCT Architecture”, IEEE DATE, Page(s):1-6, April 2007.

     pdf

 

Posters

 

· G. Karakonstantis, N. Banerjee, J. H. Choi, K. Roy, Design Paradigm for Low Power, Variation Resilient Systems using Adaptive Quality Modulation, Gigascale Systems Research Center  (GSRC) Annual Symposium,  2008.

 

· N. Banerjee, S. Ghosh, G. Karakonstantis, D. Mohapatra, J. H. Choi, K. Roy, "Yield-Centric Design Framework for Low Voltage Robust Systems” , GSRC Annual Symposium, 2007.

 

· S. Ghosh, D. Mohapatra, G. Karakonstantis, K. Roy, “CRISTA: A process-tolerant, low voltage design methodology using adaptive clocking for high-performance processors”, GSRC Annual Symposium, 2007.

 

   Diploma Thesis

 

   “Design and implementation of a hardware and software interface for an image sensor on a

    System  On Chip for image processing and video compression”,

    prof. George Stamoulis, prof. Nikolaos Bellas (Motorolla, Inc, USA), July 2005.

 

 

© gkarakon@purdue.edu

Home | Research | Publications | Teaching | Photos | Links

Georgios Karakonstantis

Phd Candidate

Electrical & Computer Enineering

Nanoelectronics Research Laboratory  ( NRL)

Purdue University

Monday, July 13, 2009