The Status Register - SREG
|
Bit |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|
|
I | T | H | S | V | N | Z | C |
SREG |
| Read/Write | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Initial Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 - I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in the interrupt mask register. If the global interrupt enable register is cleared (zero), none of the interrupts are enabled independent of the values of the interrupt mask registers. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.
The bit copy instruction BLD (Bit LoadD) and BST (Bit STore) use the T bit as source destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.
The half carry flag H indicates a half carry in some arithmetic operations.
The S-bit is always an exclusive or between the negative flag N and the two's complement overflow flag V.
Bit 3 - V: Two's Complement Overflow Flag
The two's complement overflow flag V supports two's complement arithmetics.
The negative flag N indicates a negative result in an arithmetic or logic operation.
The zero flag Z indicates a zero result in an arithmetic of logic operation.
The carry flag C indicates a carry in an arithmetic or logic operation.