The Timer/Counter Interrupt Mask Register  -  TIMSK

Bit 7  -  OCIE2:  Timer/Counter2 Output Compare Match Interrupt Enable

When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled.  The corresponding interrupt (at vector $006) is executed if a compare match in Timer/Counter2 occurs, i.e. when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

Bit 6  -  TOIE2:  Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled.  The corresponding interrupt (at vector $008) is executed if an overflow in Timer/Counter2 occurs, i.e. when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

Bit 5  -  TICIE1:  Timer/Counter1 Input Capture Interrupt Enable

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled.  The corresponding interrupt (at vector $00A) is executed if a capture triggering event occurs on PD6 (ICP), i.e. when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

Bit 4  -  OCIE1A:  Timer/Counter1 Output CompareA Match Interrupt Enable

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled.  The corresponding interrupt (at vector $00C) is executed if a CompareA match in Timer/Counter1 occurs, i.e. when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

Bit 3  -  OCIE1B:  Timer/Counter1 Output CompareB Match Interrupt Enable

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled.  The corresponding interrupt (at vector $00E) is executed if a CompareB match in Timer/Counter1 occurs, i.e. when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

Bit 2  -  TOIE1:  Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled.  The corresponding interrupt (at vector $010) is executed if an overflow in Timer/Counter1 occurs, i.e. when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

Bit 1  -  OCIE0:

 

Bit 0  -  TOIE0:  Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled.  The corresponding interrupt (at vector $012) is executed if an overflow in Timer/Counter0 occurs, i.e. when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.

 

Note:  All information on this page was taken from the ATmega16 data sheet.