ECE 456 Digital Integrated Circuit Analysis and Design (Spring 2007)
School of Electrical and Computer Engineering,
Instructor
ü Instruction hours: TTh 3:00pm~4:15pm at EE117
ü Instructor: Byunghoo Jung (765-494-2866, jungb@purdue.edu)
Ø Office hours: TTh 4:30pm~5:45pm, Room 218, MSEE Bldg, and by appointment
Text & Reference
ü Required
Text: Digital Integrated Circuits: A
Design Perspective, 2nd edition (Prentice Hall)
ü References: Principles
of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste
and K. Eshraghian, Addison Wesley
Announcements
ü Syllabus
ü 1st Midterm Exam: March 8 (Thur.)
n Ch1 ~ Ch6 Section 6.2
n In class exam / Closed book / Closed notebook / No cheat sheet
n Please bring calculator.
n Device physics equations will be provided, if required.
n Expect 4 ~ 5 problems.
ü 2nd Midterm Exam: April 12 (Thur.)
n Ch6 ~ Ch7
n In class exam / Closed book / Closed notebook / No cheat sheet
n Please bring calculator.
n Expect 4 ~ 5 problems.
ü
Final Exam: May 4th
(Fri)
n
All topics covered in
the class
n
Time: 1:00pm ~ 3:00pm
n
Room: EE117
n
Please bring
calculator
n
Expect 5~6 problems.
ü Homework
n Homework 2 Example spice code
n Homework 3 Due April 10
n Homework 4 Due April 27 Midnight
ü TSMC 0.25u CMOS technology (mosis spice parameter link)
ü BSIM manual (University of Berkeley Devices Group)
CAD
LAB
ü
Some homework problems require HSpice
simulations
ü
SUN
workstations running HSpice in MSEE
186
ü
Your accounts to access the workstations and HSpice will be enabled during the first two weeks of the
semester, and will be expired two weeks after the last day of the semester
Ø
If you want to keep your HSpice
files after the semester, you need to move or copy your files to your own
storage space
Ø
This class assumes
that the registered students have basic knowledge on UNIX commands
Ø
In case you are not
familiar with basic UNIX commands, please download a manual and get familiar with
the commands before the first homework assignment
ü
The simulation uses TSMC 0.25um model files
Ø
Please download the
model files through the link posted on the course website
Course
Outcomes (ABET):
A student who successfully
fulfills the course requirements will have demonstrated:
ü A
basic knowledge of CMOS IC processing and layout
ü An
understanding of CMOS inverter operation, both static
and dynamic
ü An
understanding of CMOS combinational logic circuit
design and analysis
ü An
understanding of basic Emitter-Coupled Logic (ECL)
design and analysis
ü An
understanding of simple BiCMOS design and analysis
ü An
understanding of basic CMOS sequential logic analysis
ü An
ability to design, layout, and analyze a simple CMOS
circuit
Grading Policy