ECE 595B CMOS Analog IC Design
Fall 2008
School of Electrical and Computer Engineering
Course/Instructor Evaluation
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> or from our home page
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> in the quicklinks on the left side of the page.
Homework
ü HW
ü Tutorials for layout and post-layout simulation: T1, T2, T3
Lab Demonstration
Session
ü Please attend one of the two sessions
Ø Tue 1:00PM~2:00PM (ENAD302F)
Ø Wed 10:00AM~11:00AM (TBA – most
likely ENAD302F)
Ø No class on Sept. 15 (Mon) in lieu of
the demonstration session
Course Information
Ø Project Description and Schedule
ü Technology used in the course design project: TSMC 0.13um CMOS technology
Ø PDK developed by NCSU
Text & Reference
ü Required
Text: Design of Analog CMOS Integrated Circuits by Behzad
Razavi (MaGraw-Hill)
ü Reference: Analog Integrated Circuit Design by David Johns and
Ken Martin (Wiley)
Instructor & TA
ü Instructor: Byunghoo Jung (765-494-2866, jungb@prudue.edu)
Ø Office hours: W 10:30AM~12:00PM, F 1:00PM~2:30PM, Room 218, MSEE Bldg, or by appointment
ü TA: Shih-Chieh Douglas Huang (sdhuang@purdue.edu)
Ø Office hours:
· TuTh 1:30PM~4:00PM (ENAD 302F)
· Anytime outside of the TA office hour in BRK1238 by appointment
Ø Facilitate and maintain the use of Lab design tools
Course
Outcomes (ABET):
A
student who successfully fulfills the course requirements will have
demonstrated:
ü An ability to analyze bias circuit using CMOS
current mirror
ü An ability to design differential operational
amplifier
ü An ability to analyze basic gm-C filter
ü Experience in oral presentation, teamwork,
and document preparation for a finished design project
Important Deadlines &
Exam Schedule
ü Project Proposal
Due: submit to the instructor (MSEE218) by
6:00PM on Sept. 17 (Wed)
ü First Exam: Oct. 10 (Fri) In class exam, close book, close notebook,
single side Letter paper with equations
1.
Practice problems: 2.13(a), 2.13(b), 2.16, 2.18, 2.24, 3.15,
3.20, 3.21, 3.27, 3.28, 4.17, 4.18, 4.21, 4.22, 5.9, 5.10, 5.13, 5.17
2.
Previous Exams: Y2006, Y2007
ü Interim Project
Report Due: submit to the instructor
(MSEE218) by 6:00PM on Oct. 22 (Wed)
ü Second Exam: Nov. 26 (Wed) In class exam, open book, open notebook
1.
Practice problems: 6.7, 6.8, 6.10, 6.12, 6.17, 7.5, 7.6,
7.7, 7.12
2.
Previous Exams: Y2006, Y2007
ü Project Report
Due: submit to the instructor (MSEE218) by
6:00PM on Dec. 15 (Mon)
ü There will be NO
final exam.
ü Submit homework and project reports to Instructor: E-mail submission is accepted and encouraged. PDF or MS-Word format only!
–
Email title AND file name rules:
• ECE595B_Homework#_$_xxxxx ( Ex: ECE595B_Homework2_B_Jung )
• ECE595B_Project_Proposal_$_xxxxx ( Ex: ECE595B_Project_Proposal_B_Jung )
• ECE595B_Project_Interim_$_xxxxx ( Ex: ECE595B_Project_Interim_B_Jung )
• ECE595B_Project_Final_$_xxxxx ( Ex: ECE595B_Project_Final_B_Jung )
• Where # is the assignment number, $ is your first name initial, and xxxxx is your last name.
•
Please use underbar not dash!
Grading Policy
ü Same scale for graduate and undergraduate students
ü Absolute and relative scale:
Ø When the average is lower than 65/100: 25% A, 40%B,
25% C, 10% D/F
Ø When the average is over 65/100: 35% A, 40% B, 20% C,
5% D/F
Ø When the average is over 75/100: 40% A, 50% B, 10% C
Ø The final grade distribution will be adjusted based on
the average and standard deviation.
ü 2 mid-terms each accounting for 25% of the grade (25% ´ 2 = 50%)
ü Design Project accounts for 40% of the grade
ü Homework assignments and Quiz account for 10%
ü Late projects or assignments will NOT be accepted
Ø You may request
extension for homework assignment or make-up exam for documented emergencies
(e.g. hospitalization, death of family member, etc.) It has to be requested BEFORE
its due date.
ü Any form of cheating will be reported to the Dean of
students AND result in a failing grade
ü Must fulfill ABET requirements to get a passing grade
CAD
LAB
ü
VLSI
CAD Lab located in MSEE189 and 360 Potter Engineering Center
ü
SUN/Linux
workstations running Cadence and HSpice (Cadence is
the default tool for your design project)
ü
Courtesy
key for after-hour access can be obtained from front desk in Potter Engineering
Library
Good Books & Resources
ü OP-amp tutorial papers
Ø James E. Solomon, “The Monolithic Op Amp: A Tutorial Study,” IEEE Journal of Solid-State Circuits, vol. sc-9, pp 314-332, Dec 1974
Ø Paul R. Grey and Robert G. Meyer, “MOS Operational Amplifiers Design – A Tutorial Overview,” IEEE Journal of Solid-State Circuits, vol. sc-17, pp 969-982, Dec. 1982
ü MOS modeling
Ø Operation and Modeling of the MOS Transistor, Yannis Tsividis, Oxford University Press; 2nd edition, 2003 (Great book on device modeling)
Ø University of Berkeley Devices Group (The inventor of the BSIM model. The class use BSIM3V3.1.)
ü Analog layout techniques
Ø The Art of Analog Layout, Alan Hastings, Prentice Hall; 2 edition, 2005
ü CMOS/Bipolar analog integrated circuit design
Ø CMOS Analog Circuit Design, Phillip E Allen, Douglas R. Holberg, Oxford University Press; 2nd edition, 2002
Ø Analysis and Design of Analog Integrated Circuits, 4th Edition, Gray, Hurst, Lewis, and Meyer, John Wiley & Sons, 4th Edition, 2001
ü Switched-capacitor circuits
Ø Analog MOS Integrated Circuits for signal processing, Roubik Gregorian and Gabor C. Temes, John Wiley & Sons, 1986
Ø
Switched
Capacitor Circuits, P.E. Allen and E. Sanchez-Sinencio, Van Nostrand
Rienhold, 1984
ü
For
advanced readers interested in integrated RF IC design for wireless
communications
Ø
RF
Microelectronics, Behzad Razavi,
Prentice Hall, 1998
Ø
The
Design of CMOS Radio-Frequency Integrated Circuits, Thomas Lee,
SW & useful links
ü MatLab- Numerical and signal processing simulation tool (student version available)
ü Simulink - Block diagram based front-end to MatLab. Powerful. Worth to use.
ü Matlab primer available here
ü Mathcad – Everyday mathtool. (student version available)
ü HSPICE manual web http://www.ee.washington.edu/class/cadta/hspice/
ü Interested students could use SWITCAP for switched capacitor simulation. But SWITCAP simulation is not required for the design project.
1. Switched capacitor circuit simulator (SWITCAP)
2. Switcap manual in PDF format (710kB)