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• Chip Design Buyers Guide
Visit our Buyers Guide
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• Interoperability
Solution Guides
Mentor Graphics Questa Vanguard Program
Synopsys Interoperability Guide
Cadence and Third Party Solution Guides
Switched Interconnect Technologies
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• Product Showcase
EdXact: Bringing Innovation Into The Verification Flow
Semiconductor Technologies > IP--Core - PLL and DLL Hard Macros
MOSAID Virtual Silicon Semiconductor IP
Carbon Design Systems' SOC-VSPT
True Circuits Product Showcase
Accelerate Forward with Poseidon Systems
PCI Express Integration and Verification
Programmable Digital Frequency Synthesizer (DFS) PLL
Develop DFM Tools. Better. Faster.
On-Demand Web Seminar Sponsored by Avnet Electronics Marketing
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• Focus Reports
Second-Tier
EDA Vendors Must Collaborate to Survive
With today's mature chip-design
flow, innovative point solutions must support multiple vendor formats and strive
to work within established standards.
Future
Verification Appears Uncertain
The EDA market is struggling to solve new
verification challenges.
Will
changes in investment patterns dampen the market rollercoaster?
Know
the Key Aspects of IP Integration
DFM
and DFY: Old Solutions to New Problems
The semiconductor industry's
shattered supply chain must be reintegrated, replacing clever point solutions
with holistic and economical flows.
Automotive
Electronics Rise To Meet Consumer Demand
With the complexity and quantity
of automotive electronics steadily increasing, designers are turning to better
EDA tools and programmable solutions.
Military
Seeks Systematic Approach to IC Design
The EDA community is focusing on
point solutions while system-level development continues to evolve.
Virtual
Prototypes Form ESL Bridge
Sometimes, the best way to understand an
abstract phrase like ESL is to focus on understanding the constituent
processes.
Analog-RF
IP Integration Challenges SoC Designers
As market forces continue to push
more analog and RF functionality into digital SoCs, designers face a host of
development issues.
Latest
Challenges & Trends in Chip Verification
The sophistication of
verification tools and techniques has increased with design complexity.
Navigating
the Silicon Jungle: FPGA or ASIC?
FPGA, structured-ASIC, and ASIC design
implementations can be differentiated by tradeoff studies and an understanding
of the basics behind each target platform.
Structured
ASICs: A Reality Check
A virtual roundtable addresses the issues
surrounding the technology
Verification
Tools
Adding more tools improves the probability of silicon success
Focus
Report: Electronic System-Level (ESL) Tools
A bolt-on to RTL or a new
methodology?
Hardware
Tools for Design
Risk reduction always comes at a cost--trial and error
will determine how much.
Focus
on Analysis Tools
To point or integrate, that is the question
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• Visit Dot.org
Learn About Important Industry Organizations
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• Find A Job
Product Development Test Engineer
Chip-to-Chip Wireless Wins SRC/SIA IC Design Challenge
Purdue, University of Minnesota, Carnegie Mellon Teams Take Top Prizes......................................................................