Graduate Publications

Following is a list of my publications published during my graduate studies at Purdue University. This list is not frequently updated and for my latest publications please visit my Google Scholar or DBLP page.

Conferences:
  • A. Raha and V. Raghunathan, “QLUT: Input-Aware Quantized Table Lookup for Energy-Efficient Approximate Accelerators”, accepted in ACM International Conference on Compilers, Architectures, and Synthesis of Embedded Systems (CASES), 2017.
  • A. Ranjan, A. Raha, V. Raghunathan, and A. Raghunathan, “Approximate Memory Compression for Energy Efficiency”, accepted in ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2017.
  • A. Raha and V. Raghunathan, “Towards Full-System Energy-Accuracy Tradeoffs: A Case Study of An Approximate Smart Camera System”, Design Automation Conference (DAC), 2017.
  • A. Raha, A. Chakrabarty, V. Raghunathan, and G. Buzzard, “Ultrafast Embedded Explicit Model Predictive Control for Nonlinear Systems”, American Control Conference (ACC), 2017.
  • A. Raha and V. Raghunathan, “Approximate Computing: A New Paradigm for Designing Energy-Efficient Systems”, IEEE/ACM International Conference on Communication Systems & Networks (COMSNETS), LNCS, 2017.
  • S. Sutar, A. Raha, V. Raghunathan, “D-PUF: An Intrinsically Reconfigurable DRAM PUF for Device Authentication in Embedded Systems”, ACM International Conference on Compilers, Architectures and Synthesis of Embedded Systems (CASES), 2016 (Best Paper Candidate).
  • H. Jayakumar, A. Raha, Y. Kim, S. Sutar, W. Lee, and V. Raghunathan, “Energy-Efficient System Design for IoT Devices”, Asia and South Pacific Design Automation Conference (ASP-DAC), 2016.
  • H. Jayakumar, A. Raha, and V. Raghunathan, “Energy-Aware Memory Mapping for Hybrid FRAM-SRAM MCUs in IoT-Edge Devices”, IEEE International Conference on VLSI Design (VLSID), 2016 (Best Paper Award).
  • A. Raha, H. Jayakumar, S. Sutar, and V. Raghunathan, “Quality-Aware Data Allocation in Approximate DRAM”, ACM International Conference on Compilers, Architectures and Synthesis of Embedded Systems (CASES), 2015.
  • A. Raha, S. Venkataramani, V. Raghunathan, and A. Raghunathan, “Quality Configurable Reduce-and-Rank for Energy Efficient Approximate Computing”, IEEE/ACM Design, Automation and Test in Europe (DATE), 2015.
  • A. Raha, S. Mitra, V. Raghunathan, and S. Rao, “VIDalizer: An Energy Efficient Video Streamer”, IEEE Wireless Communications and Networking Conference (WCNC), 2015. [Extension of ECE 595- Computer Network Systems (Spring 2013) course project].
  • H. Jayakumar, A. Raha, and V. Raghunathan, “HYPNOS: An Ultra-Low Power Sleep Mode with SRAM Data Retention for Embedded Microcontrollers”, ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (ISSS+CODES), 2014.
  • H. Jayakumar, K. Lee, W. S. Lee, A. Raha, Y. Kim, and V. Raghunathan, “Powering the Internet of Things”, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2014.
  • A. Ranjan, A. Raha, S. Venkataramani, K. Roy, and A. Raghunathan, “ASLAN: Synthesis of Approximate Sequential Circuits”, IEEE/ACM Design, Automation and Test in Europe (DATE), 2014. [Extension of ECE 595- Digital VLSI Design Automation (Spring 2013) course project].
  • A. Raha, H. Jayakumar, and V. Raghunathan, “A Power-Efficient Video Encoder using Reconfigurable Approximate Arithmetic Units”, IEEE International Conference on VLSI Design (VLSID), 2014.
  • H. Jayakumar, A. Raha, and V. Raghunathan, “QUICKRECALL: A Low Overhead HW/SW Approach for Enabling Computations across Power Cycles in Transiently Powered Computers”, IEEE International Conference on VLSI Design (VLSID), 2014.
Journals:
  • A. Raha, A. Jaiswal, S. Sarwar, H. Jayakumar, V. Raghunathan, and K. Roy, “Designing Energy-Efficient Intermittently Powered Systems using Spin Hall Effect based Non-Volatile SRAM”, IEEE Transactions on VLSI Systems, 2017.
  • S. Sutar, A. Raha, D. Kulkarni, R. Shorey, J. Tew, and V. Raghunathan, “DPUF: An Intrinsically Recon gurable DRAM PUF for Device Authentication and Random Number Generation In Embedded Systems”, ACM Transactions on Embedded Systems (TECS), 2017.
  • A. Raha and V. Raghunathan, “Synergistic approximation of computation and memory subsystems for error-resilient applications”, accepted in IEEE Embedded System Letters (ESL), 2017.
  • A. Raha, S. Sutar, H. Jayakumar, and V. Raghunathan, “Quality Configurable Approximate DRAM”, IEEE Transactions on Computers, 2016.
  • H. Jayakumar, A. Raha, and V. Raghunathan, “Energy-Aware Memory Mapping for Hybrid Memory MCUs in IoT Edge Devices”, ACM Transactions on Embedded Computing Systems, 2016.
  • A. Raha, S. Venkataramani, V. Raghunathan, A. Raghunathan, “Energy-Efficient Reduce-and-Rank using Input-Adaptive Approximations”, IEEE Transactions on VLSI Systems, 2016.
  • H. Jayakumar, A. Raha, and V. Raghunathan, “Sleep-Mode Voltage Scaling: Enabling SRAM Data Retention at Ultra-Low Power in Embedded Microcontrollers”, ACM Transactions on Embedded Computing Systems, 2016.
  • A. Raha, H. Jayakumar, and V. Raghunathan, “Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding”, IEEE Transactions on VLSI Systems, 2016 (Top Downloaded Articles) .
  • H. Jayakumar, A. Raha, W. Lee, and V. Raghunathan, “Efficiently Enabling Computations in Transiently Powered Computers”, ACM Journal of Emerging Technologies in Computing Systems, Special Issue on Advances in Design for Ultra-Low Power Circuits and Systems in Emerging Technologies, 2015.
Design Contest:
  • H. Jayakumar, A. Raha, W. S. Lee, and V. Raghunathan, “QUBE: An FRAM-based, Low Power, Modular Platform Architecture for Wireless Embedded Systems”, IEEE International Conference on VLSI Design (VLSID), 2015 (1st prize winner) .
Work-in-progress:
  • H. Jayakumar, A. Raha, and V. Raghunathan, “Energy-Aware Memory Mapping for FRAM-enabled Microcontrollers in IoT Edge Devices”, IEEE/ACM Design Automation Conference (DAC), 2015 .