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2-Dimensional Layered Materials and Devices

Transition Metal Dichalcogenide (TMD)-based Reconfigurable Devices

Utilizing a novel triple-gate design, a WSe2 device is able to operate as a tunneling field-effect transistor (TFET), a MOSFET as well as a diode, by electrostatically tuning the channel doping to the desired profile. The implementation of scaled gate dielectric and gate electrode spacing enables higher band-to-band tunneling transmission with the best observed subthreshold swing (SS) among all reported homojunction TFETs on 2D materials. This research sheds light on the potential of utilizing electrostatic doping scheme for low-power electronics and opens a path towards novel designs of field programmable mixed analog/digital circuitry for reconfigurable computing. (Images from Small, 15, 1902770, (2019))




TMD-based CMOS SRAM

A CMOS static random-access-memory (SRAM) using WSe2 as a channel material is demonstrated as potential memory implementation for flexible electronics and Internet of Things (IoT). A tri-gate design utilizing electrostatic doping is adopted for the NMOS, while an air-stable, oxygen plasma induced doping scheme is introduced to implement the PMOS. DC measurements of SRAM cells demonstrate a unique dynamic tunability enabled by modulating the n-FET doping level through electrostatically gating the extended source/drain regions. Furthermore, with various read/write assist techniques, SRAM operation at low VDD of 0.8V is achieved. (Images from 2018 IEEE International Electron Devices Meeting (IEDM), DOI: 10.1109/IEDM.2018.8614572)




Controlled Doping of TMDs Using Phythalocyanine Compounds

Surface charge transfer interaction between a family of phythalocyanine (Pc) compounds and transition metal dichalcogenides (TMDs) is explored. Comparing device characteristics of TMD field-effect transistors (FETs), we demonstrate both p-type and n-type doping of TMDs by tuning work function of the metal substitution in the Pc compound. A linear correlation between the metal work function and doping level is observed. (Images from Nanoscale, 10, 5148, (2018))




Bandgap Engineering

Bandgap engineering is a powerful technique for the design of new electronic and optoelectronic devices. Different from traditional approaches that rely on sophisticated material synthesis systems, we demonstrate that bandgap engineering is feasible in 2D layered materials through electric field control. We show that a bandgap of ~200meV can be opened in bilayer graphene (left figure), while the bandgap of bilayer MoS2 can be reduced at a rate of ~275meV per 1V/nm displacement field (right figure), to the extent that a semiconductor to metal transition can be achieved before the dielectric breakdown limit. More importantly, this spontaneous field-controlled bandgap tuning occurs during device operation, which creates a new platform to design novel electronic devices with dynamic bandwidth. (Images from Nano Research, 8, 3228 (2015) & Nano Letters, 15, 8000 (2015))


    

High Performance Cu-2D Hybrid Interconnects

Enhancing Interconnect Performance and Reliability by Replacing TaN/Ta with 2D Materials

TaN and Ta are used as the Cu diffusion barrier and liner in conventional back-end-of-line (BEOL) Cu interconnect technology. The minimum thickness of the TaN/Ta bilayer stack needs to be at least ~4 nm to maintain its capability of blocking Cu diffusion, which unavoidably occupies a substantial portion of the interconnect cross-section especially for advanced technology nodes. Since the TaN/Ta bilayer is much more resistive than Cu, the overall line resistance of the interconnect drastically increases with decreasing dimensions, which hampers its current driving capability. We have proposed and demonstrated a potential solution for the above BEOL challenge, by replacing the TaN/Ta bilayer with atomically thin 2D materials. Among various materials that we have tested (graphene, MoS2, hBN, and TaS2), the most comprehensive data were obtained on TaS2 up to date. We suggest that this BEOL compatible, low-temperature-synthesized TaS2 is not only an excellent Cu diffusion barrier, but also a desired liner. It has been projected that ultra-scaled interconnect performance can be greatly enhanced when the thick TaN/Ta bilayer is replaced by the atomically thin TaS2 to increase the percentage of Cu volume. (Images from Advanced Materials, 31, 1902397 (2019))




Low Temperature PECVD Growth of Graphene Directly on Scaled Cu Nanowires

Due to sidewall and grain boundary scattering, the resistivity of Cu at small dimensions increases rapidly, which leads to an increase in RC delay for aggressively scaled Cu interconnects and starts to negatively impact the overall system performance. We have demonstrated a novel Cu/graphene hybrid nanowire system that outperforms Cu interconnects in terms of electrical and thermal conductivity. Passivation of the Cu surface states with a 2D layered material like graphene gives rise to partially elastic surface scattering and results in enhancement in electron transport through the nanowire. We achieved 15% higher electrical conductivity, 27% higher thermal conductivity and 40% larger breakdown currents in Cu/graphene hybrid nanowires compared to pure Cu wires with the same dimensions. More importantly, the perfect sp2 bonded graphene layer serves as an ultra-thin Cu diffusion barrier that outperforms conventional Ta based barriers. (Images from Nano Letters, 15, 2024 (2015))


    

Spintronics for Deterministic and Probabilistic Logic Computing

p-bits for Probabilistic Computing (Collaborators: Appenzeller, Datta's groups)            

The probabilistic computing paradigm is based on a ^p-bit ̄ that randomly fluctuates between 0 and 1, a behavior that is mimicked by the physics of low barrier nanomagnets. A network of coupled low barrier nanomagnets traverses through its collective states and is naturally guided by the laws of statistical mechanics towards the low energy states that represent the optimal solution, thus providing hardware acceleration to a wide variety of problems in optimization, inference and machine learning. Being a classical entity, operating at room temperature, requiring robust electrical interconnections and mappable to the mature MRAM technology, probabilistic computing promises to be a viable beyond Moore computing scheme. In order to develop practical circuits with p-bits, an efficient way to implement them in hardware by leveraging spintronics technology is required. The goal of this project is the experimental realizations of p-bits and p-circuits. Shown below is a unique p-bit design based on the interaction of spin orbit torque on weak perpendicular anisotropy nanomagnets and its interesting properties as a tunable random number generator and correlated fluctuations of two such devices. (Images from Phys. Rev. B, 101(9), 094405, (2020))




TMD-based Valleytronics (Collaborators: Camsari, Upadhyaya, Gupta's groups)              

Electronic devices exploring carrier transport with spin and valley degree of freedom (DOF) have emerged as promising candidates for next-generation information storage and transport. The ability to electrically generate and detect these pure spin and valley currents is of particular importance. In recent years, electrical control of the valley DOF has just started to attract interest in two-dimensional honeycomb lattice systems, such as gapped graphene and transition metal dichalcogenides (TMDs). We find that valley current can be electrically induced and detected through the valley Hall effect (VHE) and inverse valley Hall effect (iVHE), respectively, in monolayer molybdenum disulfide (MoS2), where electronic transport is dominated by the inequivalent K and K¨ valleys of the Brillouin zone located at the edges, and carriers in these two valleys have non-zero Berry curvature due to the inherent inversion asymmetry. (Images from Science Advance, 5(4), 6478, (2019)) Moreover, several TMDs have been predicted to generate out-of-plane spins due to the unique 2D band structures, which could potentially be used in perpendicular magnetic anisotropy (PMA) deterministic switching without any additional assistance. Interestingly, opposite spins are locked to respective sub-band in each K valley of the valence band with substantially large energy splitting, which enables polarized spins to be accessible through electrical gating, and spatially separated and accumulated by electric field through VHE and iVHE, respectively. The spatial separation and accumulation of spins in these 2D TMDs are uniquely referred to as coupled valley and spin Hall effect (VSHE) and inverse coupled valley and spin Hall effect (iVSHE), respectively. We find that the electrical generation of spin current with out-of-plane polarization can be induced in monolayer tungsten diselenide (WSe2) and could be detected by a non-local spin valve structure built on graphene (Images from InfoMat, 2, 968, (2020)), making the first step towards the experimental illustration of VHSE and iVHSE in TMDs. The relevant research is still in progress.




Graphene Coating to Reduce Friction of Terminal Interfaces

Multi-layer graphene, serving as a conductive solid lubricant, is coated on the metal surface of electrical terminals. This graphene layer reduces the wear and the friction between two sliding metal surfaces while maintaining the same level of electrical conduction when a pair of terminals engage. With thin graphene layers grown by plasma enhanced chemical vapor deposition (PECVD) on Au and Ag terminals, the insertional forces can be reduced by 74% and 34% after the first cycle and 79% and 32% after the 10th cycle of terminal engagement compared with pristine Au and Ag terminals. The resistance of engaged terminals remains almost unchanged with the graphene coating.