The General Interrupt Control Register  -  GICR

Bit	7	6	5	4	3	2	1	0
	INT1	INT0	INT2	-	-	-	IVSEL	IVCE	GICR
Read/Write	R/W	R/W	R	R	R	R	R	R
Initial Value	0	0	x	0	0	0	0	0

Bit 7  -  INT1:  External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated.  The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.  Activity on the pin will cause an interrupt request even if INT1 is configured as an output.  The corresponding interrupt of External Interrupt Request 1 is executed from program memory.

Bit 6  -  INT0:  External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated.  The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) define whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed.  Activity on the pin will cause an interrupt request even if INT0 is configured as an output.  The corresponding interrupt of External Interrupt Request 0 is executed from program memory.

Bit 5  -  INT2:  External Interrupt Request 2 Enable

When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated.  The Interrupt Sense Control2 bit (ISC2) in the MCU general Control Register (MCUCSR) define whether the external interrupt is activated on rising or falling edge of the INT2.  Activity on the pin will cause an interrupt request even if INT2 is configured as an output.  The corresponding interrupt of External Interrupt Request 2 is executed from program memory.

Bits 4..0  -  Res:  Reserved Bits

These bits are reserved bits in the ATmega163 and always read as zero.