MCU Control Register  -  MCUCR

Bits 7, 5, 4  -  SM2/SM0: Sleep Mode Select Bits 2, 1 and 0

These bits select between the three available sleep modes as shown below.

SM2	SM1	SM0	Sleep Mode
0	0	0	Idle
0	0	1	ADC Noise Reduction
0	1	0	Power-down
0	1	1	Power-save
1	0	0	Reserved
1	0	1	Reserved
1	1	0	Standby
1	1	1	External Standby

Bit 6  -  SE: Sleep Enable

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed.  To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.

 

Bits 3, 2  -  ISC11/ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the GICR are set.  The level and edges on the external INT1 pin that activate the interrupt are defined in the following table.  The value on the INT1 pin is sampled before detecting edges.  If edge of toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt.  Shorter pulses are not guaranteed to generate an interrupt.  If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.

ISC11	ISC10	Description
0	0	The low level of INT1 generates an interrupt request.
0	1	Any logical change on INT1 generates an interrupt request.
1	0	The falling edge of INT1 generates an interrupt request.
1	1	The rising edge of INT1 generates an interrupt request.

Bits 1, 0  -  ISC01/ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask in the GICR are set.  The level and edges on the external INT0 pin that activate the interrupt are defined in the following table.  The value on the INT0 pin is sampled before detecting edges.  If edge of toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt.  Shorter pulses are not guaranteed to generate an interrupt.  If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.

ISC01	ISC00	Description
0	0	The low level of INT0 generates an interrupt request.
0	1	Any logical change on INT0 generates an interrupt request.
1	0	The falling edge of INT0 generates an interrupt request.
1	1	The rising edge of INT0 generates an interrupt request.