UART Control and Status Register A - UCSRA

Bit 7 - RXC:  UART Receive Complete

This bit is set when a received character is transferred from the Receiver Shift register to UDR.  The bit is set regardless of any detected framing errors.  When the RXCIE bit in UCSRB is set, the UART Receiver Complete interrupt will be executed when RXC is set (one).  RXC is cleared by reading UDR.  When interrupt-driven data reception is used, the UART Receiver Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.

Bit 6 - TXC:  UART Transmit Complete

This bit is set when the entire character (including the stop bit)  in the Transmit Shift register has been shifted out and no new data has been written to UDR.  This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receiver mode and free the communications bus immediately after completing the transmission.  When the TXCIE bit in UCSRB is set, setting of TXC causes the UART Transmit Complete interrupt to be executed.  TXC is cleared by hardware when executing the corresponding interrupt handling vector.  Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bit.

Bit 5 - UDRE:  UART Data Register Empty

This bit is set (one) when a character written to UDR is transferred to the Transmit shift register.  Setting of this bit indicates that the transmitter is ready to receive a new character for transmission.

When the UDRIE bit in UCSRB is set, the UART Transmit Complete interrupt to be executed as long as UDRE is set.  UDRE is cleared by writing UDR.  When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates.

UDRE is set (one) during reset to indicate that the transmitter is ready.

Bit 4 - FE:  Framing Error

This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero.

Bit 3 - OR:  OverRun

This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR register is not read before the next character had been shifted into the Receiver Shift register.  The OR bit is buffered, which means that it will be set once the valid data still in UDR is read.

The OR bit is cleared (zero) when the data is received and transferred to UDR.

Bit 2 - Res:  Reserved Bit

This bit is a reserved bit in the ATmega163 and will always read as zero.

Bit 1 - U2X:  Double the UART Transmission Speed

Setting this bit will reduce the division of the baud rate generator clock from 16 to 8, effectively doubling the transfer speed at the expense of robustness.  For a detailed description, see "Double Speed Transmission".

Bit 0 - MPCM:  Multi-processor Communication Mode

This bit is used to enter the Multi-Processor Communication Mode.  The bit is set when the slave MCU waits for an address byte to be received.  When the MCU has been addressed, the MCU switches off the MPCM bit, and starts data reception.

For a detailed description, see "Multi-processor Communications Mode" on page 70 of the ATmega163 datasheet.